TSP1 Host Interface

TSP1 Host Interface#

System-level overview of the host interface

System-level overview of the host interface and its interaction with the TSP1 system.#

The TSP1 host interface provides access to the state space accelerator’s inputs and outputs, enables writing of new application images into non-volatile memory (NVM), and gives users the ability to control the overall system state.

From the user’s perspective, the host interface is divided into three logical layers:

  • Physical layer and transaction protocol. The TSP1 host interface exposed through a standard SPI interface with optional “interrupt” and “wake” signals. The “interrupt” signal (INTB) is used to inform the host about buffer events; the “wake” signal is used to force the TSP1 to exit deep sleep. The TSP1 host interface defines a protocol on top of SPI that is used to access the register and buffer management layer. Future revisions of the TSP1 firmware will add support for I²C as a physical layer.

  • Register and buffer management layer. The SPI transaction protocol provides access to 128 “fast access register” slots that expose basic system information and control functionality. Another 128 register slots are reserved for “mailbox” access to 32 general-purpose FIFO buffers. Of these buffers, 28 may be assigned arbitrary application-specific roles for data input and output, including peripheral and neural network access. The first four buffers have special purposes: they are used as command and response queues and, if the corresponding functionality is activated, provide access to profiling and debug data. Buffer assignment may be flexibly configured during the application design phase.

  • Message layer. The first two buffers managed through the buffer management layer are used as command and response queue. Commands, such as starting or stopping neural network operation, are placed in the command queue. In return, the response queue informs the host about errors that may occur. The response queue is also used to signal asynchronous error information, such as ECC errors.

Convenient access to these layers, as well as usage examples, is provided through the TSP1 Software Development Kit (SDK). See the ABR developer portal https://dev.appliedbrainresearch.com/ for more information.

These three layers are described in more detail in the following chapters.