Physical Layer and Transaction Protocols

The physical layer consists of the electrical SPI connections between the TSP1 and the host system, as well as the TSP1-specific transaction protocol layered on top. In addition to the SPI signals, the TSP1 provides a low-active interrupt line (INTB) that is software-configurable to inform the host microcontroller about buffer threshold events.

The host interface is compatible with a wide variety of host systems and bridge ICs, and are designed for high throughput and compatibility with host DMA operations.

Electrical characteristics

Refer to the TSP1 datasheet for information on the electrical characteristics of the TSP1, such as permissible voltages, logic thresholds, and maximum frequencies. The description below is solely in terms of logic levels. All timings are relative to the TSP1 CPU clock speed.

In particular, ensure that the host microcontroller uses the same digital I/O voltage levels as the TSP1. Failure to do so may lead to physical damage to either device.

I²C Support

Future revisions of the TSP1 firmware will add support for I²C as a physical host interface layer. We will extend this chapter once support for I²C becomes available.

SPI

The SPI host interface is structured around transactions that are framed by the low-active chip select (TSP1_CS) signal, and a “virtual” serial shift register that resides on the TSP1. While TSP1_CS is low, and with every rising serial clock edge on the TSP1_CLK signal, a new bit originating from the host system on the TSP1_MOSI signal is shifted into this shift register. With every falling clock edge, a new bit originating from the TSP1 is shifted out of the TSP1_MISO signal. Note that TSP1_MISO only acts as a driver while TSP1_CS is low; correspondingly, the TSP1 can be used on multi-drop SPI busses where all lines except for the chip-select lines are shared.

Below, we describe the electrical interface and the bit-level signalling in more detail. We then discuss the protocol that the TSP1 layers on top of the bit-level interface. This protocol provides read and write access to TSP1 register and buffer mailbox slots.

SPI electrical interface and bit-level signalling

Physically, the SPI host interface is made up of up to six signals.

Chip Select (TSP1_CS)

This signal is a low-active input to the TSP1. A falling edge on the TSP1_CS signal starts an SPI transaction. A rising edge on TSP1_CS ends the SPI transaction. Logically, the transaction will end earlier once the number of payload bytes indicated by the TSP1 in the status phase have been transmitted. While TSP1_CS is low, the CIPO line is an active driver; while TSP1_CS is high, the chip-select signal is in high-impedance mode.

Serial clock (TSP1_CLK)

This signal carries the serial clock and is an input to the TSP1. The clock is low during inactivity (CPOL = 0). The TSP1 samples incoming bits on the rising clock edge, and outputs new bits on the falling clock edge (CPHA = 0).

Serial data in (TSP1_MOSI)

The TSP1_MOSI signal carries serial output data from the host and is an input to the TSP1. The TSP1 samples this signal on the rising TSP1_CLK edge.

Serial data out (TSP1_MISO)

The TSP1_MISO signal carries serial output data from the TSP1; it is an output from the TSP1. The TSP1 shifts new data out on the falling TSP1_CS edge, as well as on every falling edge of the TSP1_SCK line.

Interrupt (TSP1_INTB; optional)

The low-active interrupt line (INTB) informs the host about buffer events. A logic “zero” indicates that a previously configured event is pending, a logic “one” indicates that no event is pending. The TSP1_INTB line is forced high (inactive) at the end of the SPI command phase (see below). TSP1_INTB will only be pulled low again after the transaction has ended logically (see below).

Wake (TSP1_WAKE; optional)

A rising edge on this signal wakes the TSP1 from deep sleep. Please ensure a minimum pulse width of 100µs to guarantee successful wake up from sleep. Tie this signal high if power-saving functionality is not required.

SPI byte-level transaction protocol

Bit-level signalling on the SPI interface for two bytes being transferred into and out of the TSP1.

The TSP1 SPI host interface operates in 8-bit SPI mode; correspondingly, one SPI word corresponds to a single byte and transactions have byte-level granularity. Bytes that have been partially transferred before the end of the transaction are discarded. On the bit level, bytes are expected to be shifted into the TSP1 with the most significant bit (MSB) of each byte first (bit 7) and the least significant bit (bit 0) last.

Illustration of an SPI read transaction (not to scale).

Illustration of an SPI write transaction (not to scale).

There are two possible SPI transaction types: read and write transactions. Read transactions are used by the host to obtain data from the TSP1; write transactions are used to send data to the TSP1 from the host. Each transaction is split into four phases: command, delay, status, and payload. We describe these phases in more detail below.

Compatibility with host DMA controllers

From the perspective of the host system, the entire transaction with the TSP1 is designed to be “fire and forget”. That means that the host does not need to immediately react to the TSP1 response or change the number of bytes transmitted while the transaction is ongoing. The host system can queue one or multiple DMA transfers for sending and receiving data to the TSP1 and handle the responses to the transactions afterwards.

Idle output data

Whenever the TSP1_MISO signal is marked as undefined (hatched lines) in the above figures, the TSP1 outputs the “idle marker” 0xF0. This facilitates debugging connectivity issues and makes it easier to distinguish between the various protocol phases when developing code for communicating with the TSP1.

Compatibility with 32-bit host SPI modes

Although the TSP1 SPI host interface uses 8-bit SPI words, the interface is designed to be compatible with host devices that use 32-bit words for their SPI transfers, although byte-level endianness conversion is likely required. Specifically, all command phases start at four-byte boundaries in the protocol. Furthermore, since the host transmits the number of valid bytes in the command phase, the TSP1 will ignore any additional bytes that may be sent for padding purposes.

Command phase

The command phase consists of four bytes that are transmitted from the host to the TSP1. These bytes specify the operation that will be performed by the host on the TSP1. Once the command bytes have been received, the TSP1 will force the INTB signal high, i.e., indicate no active events. The TSP1 will re-evaluate whether an event is present and correspondingly update the INTB signal after the end of the transaction.

Byte index	Name	Description
0	Command	A command byte of 0x54 indicates a write transaction; a command byte of 0x55 indicates a read transaction.
1	Register index	Index of the fast access register or buffer mailbox slot that the transaction intends to read from or write to.
2	Max. payload size (bits 0-7)	The least significant byte of a 16-bit unsigned integer that indicates the maximum number of bytes that the host is attempting to read or write during the payload phase. If the host ends up sending more bytes than indicated here, then the TSP1 will ignore those bytes; this is, for example, useful if the host is using SPI in 32-bit mode and is not capable of sending fewer than four bytes at a time, but would still like to perform byte-level buffer operations on the TSP1. If the number of payload bytes is not known to the host in advance, it is always possible to set this field to 0xFFFF. The TSP1 will send the actual valid number of payload bytes in the “status” phase.
3	Max. payload size (bits 8-15)	The most significant byte of the 16-bit maximum payload size integer (see above).

Delay phase

Upon receiving the command, the TSP1 requires up to \(n_{\mathrm{delay}} = 640\) system clock cycles to react to the received command and to prepare the response. The actual time \(t_{\mathrm{delay}}\) this takes depends on the system frequency \(f_{\mathrm{sys}}\) that the TSP1 is configured to run at:

\[t_{\mathrm{delay}} = \frac{n_{\mathrm{delay}}}{f_{\mathrm{sys}}}\]

To ensure that this delay is met, the host must transmit 16 “delay bytes” of arbitrary value during the “delay phase” of the transaction protocol. This leaves enough time for the TSP1 to prepare a response at a system frequency of \(50\,\mathrm{MHz}\) and an SPI clock frequency of \(10\,\mathrm{MHz}\). If the TSP1 runs at lower frequencies, then the SPI clock must be lowered such that the time it takes to transfer the 16 bytes is greater than \(t_{\mathrm{delay}}\).

Byte index	Name	Description
4-19	Delay byte	Sixteen arbitrary bytes

Status phase

The status phase is used to convey two pieces of information: whether the TSP1 has been able to prepare a valid response to the request, and how many of the payload bytes requested in the “maximum payload size” field will actually be interpreted by the TSP1.

The host may always transmit fewer or more bytes than indicated in the “valid payload size” field. As noted above, this allows the host to opportunistically set up a DMA transfer ahead of time, without requiring a communication round-trip with the TSP1.

Byte index	Name	Description
20	Error marker 1	This byte must read as 0x00, otherwise the timing constraints described above have been violated.
21	Error marker 2	Same semantics as error marker 1.
22	Valid payload size (bits 0-7)	Least significant byte of a 16-bit unsigned integer that specifies the number of valid bytes returned by the TSP1. This number will always be less than or equal to the maximum payload size requested in the command. Fewer bytes than requested may, for example, be returned by the TSP1 if the buffer being accessed does not have the requested amount of data. Similarly, for write transactions, the valid payload size lets the host know up to which payload byte the TSP1 has consumed the payload data. For example, fewer bytes than specified may be consumed if the buffer being accessed has reached its maximum level.
23	Valid payload size (bits 8-15)	The most significant byte of the 16-bit valid payload size integer (see above).

Payload phase

Bytes 24-N form the payload phase. For read transactions, the TSP1 will shift out data bytes on the TSP1_MISO signal; for write transactions, the host must shift in data bytes on the TSP1_MOSI signal.

The host may transmit as many bytes as it sees fit; however, at most as many bytes as indicated by the TSP1 in the “valid payload size” field will actually be considered.

The SPI transaction logically ends under one of two conditions:

1. Once “valid payload size” bytes have been transmitted as payload.

2. Once a rising edge is encountered on the TSP1_CS signal.

Once the transaction ends, the TSP1 will update its internal state based on the information that has been transmitted and may signal the presence of a buffer event by pulling the INTB signal to a logic low level.

At the end of a transaction, the host must wait \(n_{\mathrm{delay}}\) cycles before starting a new transaction.

Before starting a new transaction, the host always needs to first pull the TSP1_CS signal high, and then pull it low again. This is independent of whether the transaction has already ended logically or not.