Register and Buffer Management Layer

Register space matrix for the TSP1. Individual cells correspond to a register with address 0xij, where i is the row and j is the column. Dashed boxes are reserved for future use. Cells marked with “R” are read-only.

The SPI and I2C transaction protocols provide access to the “register and buffer management layer” of the TSP1 host interface. This layer consists of up to 256 logical 32-bit “registers” (see Register space matrix for the TSP1. Individual cells correspond to a register with address 0xij, where i is the row and j is the column. Dashed boxes are reserved for future use. Cells marked with “R” are read-only. for a map of the register space) and provides access to the following services:

• Fixed status information. Registers 0x00 to 0x0F contain information about the TSP1, including the firmware and NVM image versions.

• Interrupt status and mask. Register 0x1E provides information about which buffers currently have a threshold event. The host can select which threshold events should be signalled through INTB by configuring the low-active (a “one” bit includes the buffer in the INTB generation, a “zero” bit excludes, i.e., masks, the buffer) interrupt mask in register 0x1F.

• Buffer status and control. Registers 0x20 to 0x5F provide buffer status and control functionality. This includes the current fill level, configured threshold, buffer role (input, output, etc.).

• Buffer mailbox registers. Registers 0x80 to 0xDF provide mailbox slots for reading and writing to the 32 buffers with different transactional semantics.

The register space is split into two regions:

1. Fast-access registers (0x00-0xF7). The first 128 registers provide access to system status information. Read-only registers are sorted to the beginning of this space, while read-write registers form a contiguous area at the end of the space. This memory region is presented to the host device as a “contiguous memory region”. Read transactions starting at a certain register may read more than 4 bytes at a time; the register index will auto-increment accordingly and wrap back from 0xF7 to 0x00. At most 512 bytes (i.e., all 128 registers) may be read in a single transaction. Write transactions can only modify a single register at a time.

2. Buffer mailbox registers (0x80-0xFF). These registers provide different ways to read data from or write data to one of the 32 I/O buffers. Each I/O buffer has its own mailbox register. Different sets of mailbox registers provide different transaction modes, explained in more detail below. In contrast to the “fast access register” plane, register addresses do not auto-increment. Reading more than 4 bytes from a buffer mailbox register results in more data being read from that register.

Buffers are the primary abstraction for communicating with the TSP1. Buffers are fixed-size first-in-first-out (FIFO) queues that either have an input or an output role, and are either host-managed or peripheral-managed. These roles are defined as part of the NVM image that is loaded onto the TSP1 and can, to a large degree, be freely defined during application development:

• Input buffers are used to feed data or commands for processing into the TSP1. The host can only write data to input buffers.

• Output buffers are used to obtain processed data or command responses from the TSP1. The host can only read data from output buffers.

• Host-managed buffers can be written to or read from (depending on whether the buffer is marked as input or output) through the host interface.

• Peripheral-managed buffers receive data from an I/O peripheral. To prevent unauthorised snooping of raw sensor data (e.g., data from an always-on microphone array) and thus improve end-user privacy, the host cannot freely access information in peripheral-managed buffers. The host device can at most instruct the TSP1 to discard all data in these buffers.

Below, we first discuss every available register in detail. We then, in the next section, discuss the command protocol that is layered on top of the command queue and response buffers located at the fixed buffer indices 0 and 1.

Endianness

Register contents are transmitted in little-endian byte order. That is, the least significant byte is sent first to the TSP1, whereas the most significant byte is shifted out last.

Read and write semantics

Note that the role of some registers depends on whether the host is executing a read or a write transaction. For example, the “buffer status” and “buffer control” registers share the same addresses, but the former is accessed through a read transaction, while the latter is accessed through a write transaction. Additionally, note that reads from buffer mailbox registers have side-effects. For example, reading from an output buffer mailbox may (depending on which exact mailbox is used) pull data out of the buffer.

Register Overview

The following table provides an overview of all TSP1 registers exposed through the host interface. The “R/W“ column indicates whether this register is accessed exclusively through read transactions (R), exclusively through write transactions (W), or whether the same information is available through both read and write transactions (R/W). Detailed information on the individual registers, including individual bits in status and control registers, is provided below.

Register	R/W	Name	Description
0x00	R	TSP_ID	Constant identifier to verify communication. Always reads as “TSP1” in ASCII (little-endian byte order).
0x01	R	FW_VER	Firmware or ROM version and a flag determining whether the TSP is currently booted into ROM or firmware.
0x02	R	PROTO_VER	Version of the host protocol implemented by the firmware.
0x03-0x06	R	TOOL_INFO	Information about the toolchain that produced this NVM image.
0x07-0x0A	R	CUSTOMER_INFO	16 bytes used to identify the customer who produced this NVM image.
0x0B-0x0F	R	NETWORK_INFO	16 bytes used to identify the particular neural network currently loaded onto the TSP1.
0x1E	R	IRQ_FLAGS	Buffer IRQ flags; one at bit position i indicates that the threshold condition for buffer i was met.
0x1F	R/W	IRQ_MASK	Buffer IRQ mask; one at bit position i indicates that buffer i is included in event signalling via INTB.
0x20…0x3F	R	BUFn_SIZE	Buffer n size and currently programmed IRQ threshold.
0x20…0x3F	W	BUFn_THRESHOLD	Write access to the IRQ threshold for buffer n.
0x40…0x5F	R	BUFn_STATUS	Buffer n status registers. Includes the buffer level.
0x40…0x5F	W	BUFn_CONTROL	High-level control access for buffer n. Provides functions for clearing the buffer and resetting error flags.
0x80…0x9F	R	BUFn_PULL	Pull data from output buffer n, and discard data from the buffer.
0x80…0x9F	W	BUFn_PUSH	Push data onto input buffer n.

TSP1 ID register TSP_ID

Address	Mode
0x00	Read-only

This register always reads TSP1 in ASCII (i.e., 0x31505354 encoded as little-endian).

Firmware version register FW_VER

Address	Mode
0x01	Read-only

Provides information about the firmware that is currently loaded. The individual bits in this field have the following meaning:

Bits	Name	Description
0-7	PATCH_LEVEL	Firmware patch level as a value between 0 and 255
8-15	MINOR	Firmware minor version as a value between 0 and 255
16-23	MAJOR	Firmware major version as a value between 0 and 255
24-29	Reserved
30	DEBUG	A 1 in this bit location indicates that debug functionality is currently available in firmware.
31	ROM	A 1 in this bit location indicates that the TSP1 is currently booted into the ROM bootloader, a 0 in this bit location indicates that the TSP1 is booted into firmware loaded from NVM.

Firmware build register FW_BUILD

Address	Mode
0x02	Read-only

Provides information about the flags that the firmware on the TSP was compiled with.

Bits	Name	Description
0-3	APP_MODE	Application format mode. 0x0 = GENERIC, 0x1 = ASR, 0xF = BOOTLOADER
4-7	APP_LANG	Language. 0x0 = EN, 0x1 = ZH
8-9	PCM_DATA_IN_SOURCE	Data input source for PCM in. 0x0 = PDM_RX, 0x1 = I2S_RX, 0x2 = HOST
10-15	Reserved
16-17	PROFILING_MODE	Available profiling data. 0x0 = NONE, 0x1 = MINIMAL, 0x2 = FULL
18	AUTOSTART	A 1 in this bit location indicates that the first network will start automatically.
19	MRAM_IFREN1	A 1 in this location indicates that trim data is recalled from IFREN1 instead of OTP1.
24-31	CPU_FREQ_MHZ	Frequency in MHz that the CPU is running at.

Host interface version register PROTO_VER

Address	Mode
0x03	Read-only

Provides information about the maximum host interface protocol version supported by the TSP1. Currently, this always reads as 2.

Toolchain information register TOOL_INFO

Addresses	Mode
0x04-0x07	Read-only

Provides 16 bytes of information to identify the exact version of the TSP1 toolchain that produced the NVM image.

Customer information register CUSTOMER_INFO

Addresses	Mode
0x08-0x0B	Read-only

Provides 16 bytes of information to associate the TSP NVM image with a specific customer. A value of zero indicates that this NVM image was provided by ABR.

Network information register NETWORK_INFO

Addresses	Mode
0x0C-0x0F	Read-only

Provides 16 bytes of information to identify the network currently loaded into the NVM image.

Interrupt flags register IRQ_FLAGS

Address	Mode
0x1E	Read-only

Current interrupt request (IRQ) flags for the 32 buffers. The bits in this register are independent from the mask bits configured in the IRQ_MASK register. Only host-managed buffers can generate interrupt requests.

For input buffers, a one bit at bit-location i indicates that the amount of free space in buffer i exceeds the threshold configured in the threshold register for buffer i.

For output buffers, a one bit at location i indicates that the fill level of buffer i exceeds the threshold configured in the threshold register for buffer i.

Interrupt mask register IRQ_MASK

Address	Mode
0x1F	Read or write

Mask that is applied via bit-wise AND to the IRQ_FLAGS register. If at least one bit is set in the resulting value, then an interrupt is signalled to the host by deasserting the INTB signal. Note that the INTB signal is asserted (i.e., no request is signalled) while an SPI or I2C transaction is ongoing. The INTB signal is only re-asserted once all side-effects of the last host interface transaction have been considered.

By default, the bit corresponding to the response buffer index is set. The TSP1 automatically places an ASYNC_READY message in the response buffer once it has completed its boot-up phase. The resulting IRQ may be used to kickstart communication with the TSP1.

Buffer size registers BUFn_SIZE

Addresses	Mode
0x20-0x3F	Read

Provides information about the (status) size of buffer n, as well as the configured IRQ threshold. The buffer index n is the register offset past 0x20, i.e., register 0x30 corresponds to buffer 16.

The IRQ threshold is expressed in terms of the buffer fill level. An IRQ is produced once the level is strictly greater than the threshold.

Buffers always have a power-of-two size (i.e., 2, 4, 8, 16, …, 32768). Buffers are at most 32 kiB large. The buffer size is determined by the loaded application and does not change during runtime.

Note

Size and threshold information is available for all buffers, independent of their mode. For example, the host may query information about the fill level of peripheral-managed buffers. This is useful to determine whether there is still data left that will be consumed by the neural processing unit.

Bits	Name	Description
0-15	THRESHOLD	Configured 16-bit unsigned IRQ threshold in bytes.
16-31	SIZE	Current buffer fill level in bytes as an unsigned 16-bit integer.

Buffer threshold registers BUFn_THRESHOLD

Addresses	Mode
0x20-0x3F	Write

Provides write access to the IRQ threshold of buffer n in bytes. The buffer index n is the register offset past 0x20, i.e., register 0x30 corresponds to buffer 16. Once the buffer fill level (see BUFn_LEVEL for more information) exceeds the configured IRQ threshold, the TSP1 produces an IRQ.

The threshold is clipped to the buffer size upon writing. Setting the threshold to the buffer size deactivates IRQs for this buffer.

Note

The threshold may be configured for all buffers, independent of their mode. However, only host-managed buffers will generate IRQs.

Bits	Name	Description
0-15	THRESHOLD	Configured 16-bit unsigned IRQ threshold in bytes.
16-31	Reserved	Reserved for future use. Always write zero to this value.

Buffer status registers BUFn_STATUS

Addresses	Mode
0x40-0x5F	Read

Provides status information about buffer n, including the buffer mode and its level in bytes. The buffer index n is the register offset past 0x40, i.e., register 0x50 corresponds to buffer 16.

For input buffers, the “level” is the number of bytes that can still be written to the buffer, that is, the free space in the buffer. A value of zero indicates that there is no space left in the buffer. A value equal to the size of the buffer indicates that the buffer is empty.

For output buffers, the “level” is the number of bytes that can be read from the buffer. A value of zero indicates that there is no data that can be read in the buffer. A value equal to the size of the buffer indicates that the buffer is full.

Bits	Name	Description
0	ACTIVE	Indicates whether this buffer slot is used by the currently loaded application. This bit is constant for a given application.
1	HOST_MANAGED	Set to one if this buffer is host-managed. Set to zero if the buffer is peripheral-managed.
2	INPUT	Set to one if this buffer is an input buffer, set to zero if this is an output buffer.
3	ERR_FLOW	For peripheral-managed buffers, this bit is set to one if the buffer has a peripheral-caused overflow or underflow. This has led to data loss. This bit may be cleared through the buffer control register.
4-15	Reserved	These bits are reserved for future use.
16-31	LEVEL	Buffer level in bytes.

Buffer control registers BUFn_CONTROL

Addresses	Mode
0x40-0x5F	Write

Provides control actions for buffer n. Control actions have no effect on inactive buffers, i.e., buffers that are not used by the currently loaded application. The buffer index n is the register offset past 0x40, i.e., register 0x50 corresponds to buffer 16.

Bits	Name	Description
0-15	Reserved	Reserved for future use.
15	CLEAR	Discards all buffer contents.
16-31	Reserved	These bits are reserved for future use.

Buffer pull registers BUFn_PULL

Addresses	Mode
0x80-0x9F	Read

Reading from this mailbox register pulls data from output buffer n, where n is the register offset from 0x80. As a side-effect, reading discards data from the buffer.

The number of bytes that have actually been read is communicated back to the host as part of the lower-level transaction protocol. Even if more data becomes available in the buffer while the transaction is ongoing, the number of bytes that can be read communicated back to the user at the start of the transaction is binding.

Pulling data from input buffers is not possible; attempting to do so always results in zero bytes being transferred. To discard data in an input buffer, use the CLEAR control bit provided in BUFn_CONTROL.

Buffer push registers BUFn_PUSH

Addresses	Mode
0x80-0x9F	Write

Writing to this mailbox register pushes data onto input buffer n, where n is the offset from 0x80.

The number of bytes that can be pushed onto the target buffer is determined when the transaction in the lower-level transaction protocol starts. Even if more space becomes available in the buffer while the transaction is ongoing, the amount of free space communicated back to the user at the start of the transaction is binding.

Pushing data into output buffers is not possible; attempting to do so always results in zero bytes being transferred.